Renesas Electronics Introduces Details of SDV SoC Collaboration with Honda: TSMC 3nm Process, 2000 TOPs AI Computing Power
On January 9th, Renesas Electronics, a Japanese semiconductor company, announced some technical details of the high-performance SDV (Software Defined Vehicle) SoC it has been developing in collaboration with Honda. The chip is planned for use in future Honda 0 series electric vehicles, particularly for models to be launched at the end of this decade.
This SoC utilizes TSMC's 3nm automotive process technology, likely a variant of the N3A process, and combines Renesas' general-purpose fifth-generation R-Car X5 SoC with an AI accelerator developed by Honda. It offers 2000 TOPs AI computing power and has an energy efficiency of 20 TOPs/W, providing the AI performance needed for advanced functions like autonomous driving while maintaining low power consumption.
Renesas stated that Honda 0 electric vehicles will adopt a centralized E/E (electrical/electronic) architecture, controlling various vehicle functions with a single ECU (Electronic Control Unit). The core EUC SoC, developed in collaboration by the two companies, will be the 'heart' of the SDV, managing basic vehicle operations such as ADAS, autonomous driving, powertrain control, and comfort functions.
